1. Technical Field
The present invention relates to integrated circuits, and more specifically to a static random access memory device.
2. Description of the Related Art
In general, semiconductor memories may be divided into two types, volatile memories and non-volatile memories. Volatile memories lose stored data when power is removed while non-volatile memories retain stored data when power is removed. The most basic part of a semiconductor memory is the data storage cell, which can be anything that can store two well defined states in a specified and repeatedly accessible location. In semiconductor memories, the most common storage device elements are either a latch or a capacitor. When a memory bit is stored in a latch, or a big-stable flip-flop, the cell is said to be static cell because it does not require its data to be refreshed as long as power is applied to the cell. Latched semiconductor storage cells are big-stable transistor flip-flops in various configurations. Semiconductor flip-flops can be made using either metal oxide semiconductor (MOS) or bipolar transistors.
Static random access memory (SRAM) cells are volatile memory cells. SRAM memory cells are generally either four transistor or six transistor memory cells. Each SRAM cell is coupled to a bit line pair and to a word line. Data is read from or written into a selected SRAM cell via the bit line pair. SRAMS are generally used in applications requiring high speed operations, such as a cache memory for a data processing system. Unlimited numbers of write operations can be performed on an SRAM without reducing reliability.
As can be seen with reference to FIG. 1, static random access memory cell 100 includes two load elements L1 and L2 and two storage transistors T1 and T2. Additionally, two access transistors T3 and T4 are included to access SRAM cell 100. In FIG. 1, the transistors are MOS transistors with load devices L1 and L2, which may be, for example, depletion mode transistors in a NMOS cell. The load devices are typically PMOS transistors in a CMOS cell and load resistors are used in a mix-MOS or R-load cell. Typically, storage transistors T1 and T2 and access transistors T3 and T4 are enhancement type NMOS transistors. Power is provided to cell 100 by connecting load elements L1 and L2 to an upper power supply voltage VCC and the drains of transistors T1 and T2 to a lower power supply voltage VSS.
Data is stored as voltage levels within the two sides of the flip-flop in opposite voltage configurations. In other words, node A is high when node B is low in one state and node A is low when node B is high in a second state, resulting in two stable states.
When loads L1 and L2 are p-channel pull-up transistors connected to an upper power supply voltage, Vcc, the busing requirements use to route Vcc throughout the memory array requires significant amounts of real estate on the chip and becomes a key limitation of cell size scaling in static random access memory cells. Therefore, it would be advantageous to have an improved SRAM cell in which scaling limitations caused by the routing of the upper power supply voltage to cells is reduced.